1. Field of the Invention
The present invention relates to a semiconductor device, which applies flip-chip connection, and a manufacturing method of the same.
2. Description of the Related Art
In recent years, the flip-chip connection is being used as a mounting method involving a short connection length of wiring to comply with a trend of multiplication of pins, a provision of a finer pitch, speeding up of a signal speed, high heat generation and the like of a semiconductor element (e.g., Japanese Patent Laid-Open Applications No. HEI 8-45938, No. HEI 9-205096 and No. 2001-93928). The semiconductor element used for the flip-chip connection has, for example, electrode pads which are formed to have an area shape and metal bumps such as solder bumps which are formed on the electrode pads. Meanwhile, a substrate on which the semiconductor element is mounted has electrode pads which are formed in position corresponding to the electrode pads of the semiconductor element.
The flip-chip connection is a method of connecting the semiconductor element and the electrode pads of the substrate by aligning the semiconductor element and the electrode pads of the substrate and heating to melt the solder bumps. Generally, a flux agent is coated onto the substrate or the semiconductor element to reduce the oxide film of the solder bumps and mounting the semiconductor element in position on the substrate by means of a bonder. Then, the solder bumps are connected by heating to melt in a reflow furnace. The flux agent is washed, a resin agent is filled and cured in the gap between the substrate and the semiconductor element to seal them. Thus, the flip-chip connection is completed by through above steps.
To comply with the semiconductor element which is being made to have a finer pitch and additional speeding up, application of Cu wiring which realizes lowering of resistance of wires and an insulator film (low-k film) with a low dielectric constant, which decreases capacitance between wires, is being proceeded (e.g., Japanese Patent Laid-Open Application No. 2003-68740). As a material (low-k material) configuring a low dielectric constant insulating film, it is being studied to use, for example, silicon oxide (SiOF) doped with fluorine, silicon oxide (SiOC) doped with carbon, organic silica, a porous body of them, or the like. But, the low-k material has a drawback that it is poor in mechanical strength and adhesion strength. Therefore, a crack, peeling or the like occurs easily in the low-k film itself or the interface in the flip-chip connection step.
The cause of the crack or peeling occurring in the low-k film or its interface includes a difference in thermal expansion coefficient between the semiconductor element and the substrate in the step of heating to melt the solder bumps. Specifically, the semiconductor element has a thermal expansion coefficient of about 3 ppm, while the substrate has a thermal expansion coefficient larger than that of the semiconductor element, and particularly a resin-based substrate has a thermal expansion coefficient of 10 ppm or more. Such a difference in thermal expansion coefficient results in deformation of the solder bumps in the step of heating to melt the solder bumps and the subsequent cooling step. Generally, the deformation of the solder bumps does not disturb the connection because the pads have a large diameter of about 100 μm and a self-align effect or the like also acts on it.
But, the low-k film is poor in mechanical strength and adhesion strength, so that a crack, peeling or the like is easily caused by a stress produced because of deformation or the like of the solder bumps. Thus, the semiconductor element to which the low-k film is applied is effective to have fine pitched wiring, speeding up and the like but has a drawback that a crack, peeling or the like occurs easily because the low-k film is poor in mechanical strength and adhesion strength. Such a crack, peeling or the like because of the low-k film is a cause of degrading the production yield and reliability of the semiconductor device which applies the flip-chip connection.
Besides, a general Sn—Pb solder was often used for the solder bumps which are used for the flip-chip mounting. But, it is now demanded to decrease the used amount of lead (Pb), which is worried about its load on the environment and effects on the human body, in various types of fields. Therefore, the application of a solder material not containing Pb, e.g., Sn—Ag type solder, Sn—Bi type solder or the like, is also being expanded in the field of electronic parts. But, a solder material (Pb-free solder) not containing Pb has a melting point higher than that of the Sn—Pb solder and a stress based on a temperature difference between a heating-to-melt temperature and a cooling-to-cure temperature increases. Therefore, the occurrence of a crack, peeling or the like because of the low-k film becomes more conspicuous. In addition, the Pb-free solder may be harder than the Sn—Pb solder, and a stress easing effect by the solder bumps becomes low. This point is also a cause of increasing a rate of incidence of a crack, peeling or the like of the low-k film.